Circuit Elements
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    Circuit Elements
    Properties
    Timediagram
    1 cycle = Units
    Quick Menu
    Please switch to the landscape mode and refresh to access the simulator
    Layout Elements
    Timing Diagram
    1 cycle = Units
    Testbench
    Test: Type:
    Group:
    Case:
    LABELS
    Bitwidth
    Current Case
    Result
    placeholder Tests Passed View Detailed

    No Test is attached to the current circuit

    Verilog Module
    This is an experimental module. The code is not saved unless the "Save Code" button is clicked.
    Apply Themes

    Select a theme:

    Properties
    Layout
    Width
    Height
    Reset all nodes:
    Title
    Title Enabled:
    • Paste
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    • New Circuit
    • Insert SubCircuit
    • Center Focus
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